ℹ️ Introduction

iWeaver AI summarizes the content of this PDF arXiv:2408.06390 [pdf, other] to help you improve your efficiency 100 times.

📖 The Summary Content is:

Title

• Document Title: Approximate ADCs for In-Memory Computing

Authors and Affiliations

• Authors: Arkapravo Ghosh, Hemkar Reddy Sadana, Mukut Debnath, Panthadip Maji, Shubham Negi, Sumeet Gupta, Mrigank Sharad, Kaushik Roy
• Affiliations: Indian Institute of Technology Kharagpur, Purdue University

Abstract

• The paper discusses the challenges of using ADCs in In-Memory Computing (IMC) architectures for deep learning accelerators, which consume a significant amount of power and area.
• Proposes a peripheral aware design to mitigate the overheads by incorporating ADC non-idealities in the training of deep learning models.

Keywords

• In-memory computing, deep learning, low power, VLSI, mixed signal

Introduction

• Deep Neural Networks (DNNs) require extensive dot-product calculations, which can be efficiently organized as matrix-vector-multiplication (MVM) operations in IMC.
• IMC reduces data traffic between memory and processors by storing kernel weights in memory arrays.

In-Memory Computing Macro

• Describes the IMC scheme based on SRAM, including current-mode and charge-mode MVM computation.
• Discusses the mapping of DNN onto IMC SRAM Macro with ADC based readout and the challenges of ADC resolution requirements.

ADC for IMC Operation

• Explains the use of transimpedance stages or current integrator stages for converting output current into a proportional voltage for ADCs in current-mode IMC.
• Mentions the use of Single Slope ADC (SS-ADC) and Successive Approximation Register ADC (SAR-ADC) for current-mode IMCs.

CCO-Based ADC for IMC Macro

• Presents the design and analysis of a current-controlled oscillator (CCO) based ADC for IMC, which is simple, compact, and suitable for column-parallel operation.

• Introduces a framework that addresses non-idealities of ADCs along with SRAM and crossbar interconnects through a modeling approach using neural networks.

Conclusion

• The paper concludes that the proposed variation aware training approach can significantly relax the design constraints for read-out ADCs in IMC, allowing for more compact units and facilitating circuit-architecture-algorithm co-design for DNN accelerators.

References

• Lists various references related to IMC, deep learning, and ADC design, indicating the breadth of research in the field.

‍

‍

                                                               Contents summarized by iWeaver AI

❓Q&A

You can ask iWeaver questions about the summary content

1. What is the primary challenge with ADCs in In-Memory Computing (IMC) architectures for deep learning accelerators?
   • The primary challenge is that ADCs required for reading out the MVM results consume more than 85% of the total compute power and dominate the area, which negates the benefits of the IMC scheme.
2. How does the proposed peripheral aware design aim to mitigate the overheads associated with ADCs in IMC units?
   • The peripheral aware design incorporates the non-idealities of ADCs in the training of the deep learning models, along with those of the memory units. This approach is intended to simplify the design of mixed-signal IMC units.
3. What are the potential benefits of the proposed variation aware training (VAT) scheme for IMC architectures?
   • The VAT scheme can significantly relax the design constraints for read-out ADCs, allowing for more compact units. It is also applicable to different IMC schemes and ADC topologies, facilitating a circuit-architecture-algorithm co-design approach for DNN accelerators based on IMC.

‍

📊 iWeaver AI Can Generate Mind Map

‍

‍